IA-32 architecture configuration control registers
Only various processors based on Cyrix CPU cores support CCRs. These registers
are the ancestors to nowaday's MSRs. They can be accessed
through port 22h (index) and port 23h (data), using IN and OUT instructions. To
read a CCR, the register's index must be sent to port 22h, before the current
register value can be read from port 23h. Similarily, to write a CCR, the index
must be written to port 22h, before the desired register value can be written
to port 23h.
If the value sent to port 22h (by an OUT instruction) does match a valid CCR
index, then the processor will not issue an I/O cycle on its external bus.
Instead it expects a subsequent IN from or OUT to port 23h. Since the CCRs do
reside within the processor, no I/O delay should be required. However, older
documentation contained sample code with I/O delays. Finally, the CCRs should
not be accessed unless a Cyrix core-based processor has been detected.
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
10h |
CESR |
0001b |
Control and Event Select Register? |
no |
yes |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (select PeMo event(s)?) |
no |
yes |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
18h |
PMC0 |
0001b |
Performance Monitoring Counter 0? |
no |
yes |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (PeMo counter?) |
no |
yes |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
19h |
PMC1 |
0001b |
Performance Monitoring Counter 1? |
no |
yes |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (PeMo counter?) |
no |
yes |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
1Ah |
PMC2 |
0001b |
Performance Monitoring Counter 2? |
no |
yes |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (PeMo counter?) |
no |
yes |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
1Bh |
PMC3 |
0001b |
Performance Monitoring Counter 3? |
no |
yes |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (PeMo counter?) |
no |
yes |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
20h |
PCR |
0001b |
Performance Control Register |
yes |
no |
no |
|
|
bit |
name |
description |
7 |
LSSER |
load/store serialization (0=disabled, 1=enabled) |
yes |
no |
no |
6 |
BTB_TR |
BTB Test Register access TR1/TR2 (0=disabled, 1=enabled) |
yes |
no |
no |
5 |
reserved |
reserved |
yes |
no |
no |
4 |
MLR |
misaligned load reordering (0=disabled, 1=enabled) |
yes |
no |
no |
3 |
AIS |
all instruction stalled to serialize pipe (0=disabled, 1=enabled) |
yes |
no |
no |
2 |
LOOP_EN |
no prefetch flush if present destination (0=disabled, 1=enabled) |
yes |
no |
no |
1 |
BTB_EN |
branch target buffer (0=disabled, 1=enabled) |
yes |
no |
no |
0 |
RSTK_EN |
return stack (0=disabled, 1=enabled) |
yes |
no |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
30h |
DBR0 |
0001b |
Debug Register 0 |
no |
yes |
yes |
|
|
bit |
name |
description |
7 |
MATCH? |
initiate DBR1..DBR3 and DOR use by clearing this bit |
no |
yes |
yes |
6 |
BTB_TR |
BTB TR1/TR2 access (0=disabled, 1=enabled) |
no |
yes |
yes |
5 |
BYP_FORW |
data bypassing and forwarding (0=disabled, 1=enabled) |
no |
yes |
yes |
4..0 |
unknown |
unknown |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
31h |
DBR1 |
0001b |
Debug Register 1 |
no |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (set to B8h/F8h during LOOP/XCHG patch) |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
32h |
DBR2 |
0001b |
Debug Register 2 |
no |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (set to 7F/7Fh during LOOP/XCHG patch) |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
33h |
DBR3 |
0001b |
Debug Register 3 |
no |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown (set to 00h/00h during LOOP/XCHG patch) |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
34h |
? |
0001b |
unknown |
no |
yes |
? |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
yes |
? |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
38h |
? |
0001b |
unknown |
no |
yes |
? |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
yes |
? |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
3Ch |
DOR |
0001b |
Debug Opcode Register |
no |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
OPCODE |
1st byte of opcode(s) which should serialize (using DBR1..3)
(set to E2h/87h during LOOP/XCHG patch)
|
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
60h |
? |
0001b |
unknown |
yes |
no |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
yes |
no |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
61h |
? |
0001b |
unknown |
yes |
no |
no |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
yes |
no |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
C0h |
CCR0 |
don't care |
Configuration Control Register 0 |
no |
yes |
yes |
|
|
bit |
name |
description |
7 |
SUSP #1 |
SUSPI# and SUSPA# pins (0=disabled, 1=enabled) |
no |
no |
no |
6 |
CO #1 |
cache organization (0=two-way set assoc., 1=direct mapped) |
no |
no |
no |
5 |
BARB #1 |
writeback of dirty lines on HOLD (0=disabled, 1=enabled) |
no |
no |
no |
4 |
FLUSH #1 |
FLUSH# input pin (0=disabled, 1=enabled) |
no |
no |
no |
3 |
KEN #1 |
KEN# input pin (0=disabled, 1=enabled) |
no |
no |
no |
2 |
A20M #1 |
A20M# input pin (0=disabled, 1=enabled) |
no |
no |
no |
1 |
NC1 |
640..1MB not cacheable (0=disabled, 1=enabled) |
no |
yes |
yes |
0 |
NC0 #1 |
HMA caching for real/V86 mode (0=disabled, 1=enabled) |
no |
no |
no |
note |
#1 |
These bits are only available for 80486SLC/80486DLC processors. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
C1h |
CCR1 |
don't care |
Configuration Control Register 1 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7 |
SM3 |
ARR3 refers to SMM space (0=disabled, 1=enabled) |
no |
yes |
yes |
6..5 |
reserved |
reserved |
yes |
yes |
yes |
4 |
NO_LOCK |
negate LOCK# pin (0=disabled, 1=enabled) |
no |
yes |
yes |
3 |
MMAC |
memory access from inside SMM (0=disabled, 1=enabled) |
yes |
no |
no |
2 |
SMAC |
SMRAM access from outside SMM (0=disabled, 1=enabled) |
yes |
yes |
yes |
1 |
USE_SMI |
SMI# and SMIACT# pins (0=ignored/disabled, 1=enabled) |
yes |
yes |
yes |
0 |
RPL #1 |
RPLSET1/0 and RPLVAL# pins (0=floating, 1=enabled |
no |
no |
no |
note |
#1 |
This bit is only available for pre-5x86 processors. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
C2h |
CCR2 |
don't care |
Configuration Control Register 2 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7 |
USE_SUSP |
SUSP# and SUSPA# pins (0=ignored/floats, 1=enabled) |
yes |
yes |
yes |
6 |
BWRT |
burst write cycles (0=disabled, 1=enabled) |
yes |
no |
no |
5 |
BARB #1 |
writeback of dirty lines on HOLD (0=disabled, 1=enabled) |
no |
no |
no |
4 |
WT1 |
5x86: 640..1MB write through (0=disabled, 1=enabled) |
yes |
yes |
yes |
WPR1 |
M1/M2: 640..1MB write prot. (0=disabled, 1=enabled) |
3 |
SUSP_HLT |
low power suspend mode on HLT (0=disabled, 1=enabled) |
yes |
yes |
yes |
2 |
LOCK_NW |
CR0.NW read only (0=disabled, 1=enabled) |
yes |
yes |
yes |
1 |
USE_WBAK |
5x86: use write back interface (0=disabled, 1=enabled) |
yes |
yes |
yes |
SADS |
M1/M2: slow ADS# (0=disabled, 1=enabled) |
0 |
COP #2 |
coprocessor interface pins BUSY#, PEREQ, and ERROR#
(0=disabled, 1=enabled)
|
no |
no |
no |
notes |
#1 |
This bit is only available for pre-5x86 processors. The CCR2 is not available for 80486SLC/DLC processors. |
#2 |
This bit is only available for 486S and 486S2 processors. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
C3h |
CCR3 |
don't care |
Configuration Control Register 3 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7..4 #1 |
MAPEN |
access to other CCRs than C0..CFh, FEH, and FFh
(0000b=disabled, 0001b=enabled)
|
yes |
yes |
yes |
3 |
SMM_MODE |
Intel 80486SL SMM emulation (0=disabled, 1=enabled) |
yes |
no |
no |
2 |
LINBRST |
linear burst mode (0=disabled, 1=enabled) |
yes |
yes |
yes |
1 |
NMI_EN |
NMI recognition in SMM (0=disabled, 1=enabled) |
yes |
yes |
yes |
0 |
SMI_LOCK |
prevent modifications of CCR1.USE_SMI, SMAC, MMAC, M3,
and CCR3.NMI_EN, SMM_MODE, and SMAR or ARR3 outside
SMM, cleared by processor RESET (0=disabled, 1=enabled)
|
yes |
yes |
yes |
note |
#1 |
If MAPEN0 (bit 4) can be toggled, then the processor supports the DIR0 and DIR1 registers. |
name |
MAPEN? |
5x86 |
M1 |
M2 |
base address #1 |
block size |
for NCR0..3, SMAR, ARR0..6 |
for ARR7 |
A32..24 |
A23..16 |
A15..12 |
bit 7..0 |
bit 7..0 |
bit 7..4 |
bit 3..0 |
|
xh |
NCR0 #2 |
don't care |
no |
no |
no |
C4h |
C5h |
C6h |
|
0h |
disabled |
disabled |
NCR1 #2 |
don't care |
no |
no |
no |
C7h |
C8h |
C9h |
1h |
4 KB |
256 KB |
NCR2 #2 |
don't care |
no |
no |
no |
CAh |
CBh |
CCh |
2h |
8 KB |
512 KB |
NCR3 #2 |
don't care |
no |
no |
no |
CDh |
CEh |
CFh |
3h |
16 KB |
1 MB |
ARR0 |
don't care |
no |
yes |
yes |
C4h |
C5h |
C6h |
|
4h |
32 KB |
2 MB |
ARR1 |
don't care |
no |
yes |
yes |
C7h |
C8h |
C9h |
5h |
64 KB |
4 MB |
ARR2 |
don't care |
no |
yes |
yes |
CAh |
CBh |
CCh |
6h |
128 KB |
8 MB |
SMAR/ARR3 |
don't care |
yes #3 |
yes |
yes |
CDh |
CEh |
CFh |
7h |
256 KB |
16 MB |
ARR4 |
0001b |
no |
yes |
yes |
D0h |
D1h |
D2h |
8h |
512 KB |
32 MB |
ARR5 |
0001b |
no |
yes |
yes |
D3h |
D4h |
D5h |
9h |
1 MB |
64 MB |
ARR6 |
0001b |
no |
yes |
yes |
D6h |
D7h |
D8h |
Ah |
2 MB |
128 MB |
ARR7 |
0001b |
no |
yes |
yes |
D9h |
DAh |
DBh |
Bh |
4 MB |
256 MB |
notes |
#1 |
This defines the upper 20 physical address bits of the region. |
|
Ch |
8 MB |
512 MB |
#2 |
These NCR0..3 are only available for 80486SLC/DLC processors. |
Dh |
16 MB |
1 GB |
#3 |
The SMAR is also available for pre-5x86 processors (acts like ARR3). |
Eh |
32 MB |
2 GB |
#4 |
The block size is 4 KB instead of 4 GB for SMAR (but not ARR3). |
Fh |
4 GB #4 |
4 GB |
NCR0..3 |
Non Cacheable Region 0..3 |
These define 80486SLC/DLC non-cacheable memory regions. |
SMAR |
SMM Address Region |
This register defines the SMRAM memory region for pre-M1s. |
ARR0..7 |
Address Region Register 0..7 |
These registers define memory regions for M1/M2s. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
DCh .. E3h |
RCR0 .. RCR7 |
0001b |
Region Configuration Register 0..7 #1 |
no |
yes |
yes |
bit |
name |
description |
7 |
reserved |
reserved |
no |
yes |
yes |
|
|
6 |
INV_RGN |
apply RCR to all memory addresses outside the region
specified by the corresponding ARR, for RCR0..6 only
(0=disabled, 1=enabled)
|
no |
no |
yes |
5 |
NLB |
negate LBA# (0=disabled, 1=enabled) |
no |
yes |
no |
4 |
WT |
write through cacheing (0=disabled, 1=enabled) |
no |
yes |
yes |
3 |
WG |
write gathering (0=disabled, 1=enabled) |
no |
yes |
yes |
2 |
WL |
weak locking (0=disabled, 1=enabled) |
no |
yes |
yes |
1 |
WWO |
weak write ordering (0=disabled, 1=enabled) |
no |
yes |
no |
0 |
RCD |
RCR0..6: region non-cacheable (0=disabled, 1=enabled) |
no |
yes |
yes |
RCE |
RCR7: region cacheable (0=disabled, 1=enabled) |
note |
#1 |
These registers contain the attributes of the memory regions, defined by ARR0..7. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
E8h |
CCR4 |
0001b |
Configuration Control Register 4 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7 |
CPUID |
EFLAGS.ID and CPUID instruction (0=disabled, 1=enabled) #1 |
yes |
yes |
yes |
6 |
TOGGLE |
toggle burst cycle address sequence (0=disabled, 1=enabled) |
no |
yes #2 |
yes |
5 |
FP_FAST |
fast FPU exception reporting (0=disabled, 1=enabled) |
yes |
no |
no |
4 |
DTE_EN |
directory table cache (0=disabled, 1=enabled) |
yes |
yes |
no |
3 |
MEM_BYP |
memory bypassing (0=disabled, 1=enabled) |
yes |
no |
no |
2..0 |
IORT |
I/O recovery time (default is 25=32) #3 |
yes |
yes |
yes |
notes |
#1 |
The bit, EFLAGS.ID, and CPUID are only available for 5x86 processors with a DIR1 value of 1xh or later.
|
#2 |
The M1 processor does not support this bit. Only the M1L processor does. |
#3 |
The following values are possible: 0=no delay, 1..6=2n clocks, or 7=128 clocks (5x86) or no delay (M1/M2). |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
E9h |
CCR5 |
0001b |
Configuration Control Register 5 |
no |
yes |
yes |
|
|
bit |
name |
description |
7 |
reserved |
reserved |
no |
yes |
yes |
6 |
VIPERM |
no access to other CCRs than C0..CFh if MAPEN<>0001b
(0=disabled, 1=enabled) #1
|
no |
yes |
yes |
5 |
ARREN |
ARR0..7 (0=disabled, 1=enabled) #2 |
no |
yes |
yes |
4 |
LBR1 |
640..1MB with LBA# (0=disabled, 1=enabled) |
no |
yes |
no |
3..2 |
reserved |
reserved |
no |
yes |
yes |
1 |
SLOP |
slow down LOOP instruction (0=disabled, 1=enabled) #3 |
no |
yes |
no |
0 |
WT_ALLOC |
allocate new cache lines on write (0=disabled, 1=enabled) |
no |
yes |
yes |
notes |
#1 |
This disables DIR0 and DIR1. The CPUID level #1 will return FFh in AH then. |
#2 |
If CCR1.SM3 is set, then ARR3 is enabled regardless of the ARREN setting. |
#3 |
This bit is only available for M1 processors with a DIR1 value of 17h..21h. Also refer to DBR0..3 and DOR. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
EAh |
CCR6 |
0001b |
Configuration Control Register 6 |
no |
no |
yes |
|
|
bit |
name |
description |
7 |
reserved |
reserved |
no |
no |
yes |
6 |
N |
Cyrix enhanced SMM nested SMIs (0=disabled, 1=enabled) #1 |
no |
no |
yes |
5..2 |
reserved |
reserved |
no |
no |
yes |
1 |
WP_ARR3 |
SMRAM write prot. outside SMM (0=disabled, 1=enabled) |
no |
no |
yes |
0 |
SMM_MODE |
Cyrix enhanced SMM (0=disabled, 1=enabled) |
no |
no |
yes |
note |
#1 |
This bit is cleared upon entry to every SMM routine, and set upon every RSM. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
EBh |
CCR7 |
0001b |
Configuration Control Register 7 |
no |
no |
yes |
|
|
bit |
name |
description |
7 |
PGE |
PGE flag for CPUID level #1 (0=enabled, 1=disabled) |
no |
no |
yes |
6..3 |
reserved |
reserved |
no |
no |
yes |
2 |
MMX_RES |
unknown |
no |
no |
yes |
1 |
MMX_RES |
unknown |
no |
no |
yes |
0 |
MMX_PLUS |
extended MMX instructions (1=enabled, 0=disabled) |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
ECh |
? |
0001b |
unknown |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
EDh |
? |
0001b |
unknown |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
EEh |
? |
0001b |
unknown |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
EFh |
? |
0001b |
unknown |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
??h |
CSECTM |
0001b |
Cache Sector Map Register |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
unknown |
unknown |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
F0h |
PMR |
0001b |
Power Management Register |
yes |
no |
no |
|
|
bit |
name |
description |
7 |
SMC_CHK |
no self-modifying code checking (0=disabled, 1=enabled) |
yes |
no |
no |
6..3 |
reserved |
reserved |
yes |
no |
no |
2 |
HLF_CLK |
core at 1/2 bus speed if bus is idle (0=disabled, 1=enabled) |
yes |
no |
no |
1..0 |
CLK |
clock multiplier (00b=1.0x, 01b=2.0x, 10b=3.0x, 11b=4.0x) |
yes |
no |
no |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
FBh |
DIR2 |
0001b |
Device Identification Register 2 |
no |
no |
yes |
|
|
bit |
name |
description |
7..0 |
SUBREV |
sub-revision |
no |
no |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
FCh |
DIR3 |
0001b |
Device Identification Register 3 |
no |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
FAMILY |
processor family which will be returned by CPUID level #1 |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
FDh |
DIR4 |
0001b |
Device Identification Register 4 |
no |
yes |
yes |
|
|
bit |
name |
description |
7..4 |
MODEL |
processor model which will be returned by CPUID level #1 |
no |
yes |
yes |
3..0 |
STEP |
processor step which will be returned by CPUID level |
no |
yes |
yes |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
FEh |
DIR0 |
don't care |
Device Identification Register 0 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7..0 |
DEVICE |
00h=80486SLC, 01h=80486DLC
02h=80486SLC2, 03h=80486DLC2
04h=80486SRx, 05h=80486DRx
06h=80486SRx2, 07h=80486DRx2
08h=80486SRu, 09h=80486DRu
0Ah=80486SRu2, 0Bh=80486DRu2
10h=80486S, 11h=80486S2
12h=80486Se, 13h=80486S2e
1Ah=80486DX, 1Bh=80486DX2, 1Fh=80486DX4
41h=MediaGX GX (3.0x mode)
45h/47h=MediaGX GX (3.0x mode)#1
44h/46h=MediaGX GX (4.0x mode)
40h/42h=MediaGX GXm (4.0x mode)
47h=MediaGX GXm (5.0x mode)
41h/43h=MediaGX GXm (6.0x mode)
44h/46h=MediaGX GXm (7.0x mode)
45h=MediaGX GXm (8.0x mode)
FFh=very likely not a Cyrix/IBM processor
|
n/a |
n/a |
n/a |
28h/2Ah: 5x86 (1.0x mode), 29h/2Bh: 5x86 (2.0x mode)#1
2Dh/2Fh: 5x86 (3.0x mode), 2Ch/2Eh: 5x86 (4.0x mode)
30h/32h: M1 (1.0x mode), 31h/33h: M1 (2.0x mode)
35h/37h: M1 (3.0x mode), 34h/36h: M1 (4.0x mode)
50h/58h: M2 (1.0x mode), 51h/59h: M2 (2.0x mode)
52h/5Ah: M2 (2.5x mode), 53h/5Bh: M2 (3.0x mode)
54h/5Ch: M2 (3.5x mode), 55h/5Dh: M2 (4.0x mode)
56h/5Eh: M2 (4.5x mode), 57h/5Fh: M2 (5.0x mode)
|
yes |
yes |
yes |
note |
#1 |
The first value refers to a "S" part, while the second value refers to a "P" part. It is unknown what exactly that means. |
# |
name |
MAPEN? |
description |
5x86 |
M1 |
M2 |
FFh |
DIR1 |
don't care |
Device Identification Register 1 |
yes |
yes |
yes |
|
|
bit |
name |
description |
7..4 |
STEP |
processor stepping |
yes |
yes |
yes |
3..0 |
REV |
processor revision |
yes |
yes |
yes |
|