IA-32 architecture coherency
serializing instructions and events |
doc? #1 |
instruction or event |
486? #2 |
use? #3 |
description and comments |
yes |
IRET(D) |
yes |
yes |
may be privileged under some circumstances |
yes |
RSM |
yes |
yes |
can only be executed from within SMM |
yes |
CPUID |
no |
no |
non-privileged |
yes |
LGDT Ms |
no |
no |
privileged |
yes |
LIDT Ms |
no |
no |
privileged |
yes |
LLDT Ew |
no |
no |
privileged |
yes |
LTR Ew |
no |
no |
privileged |
yes |
INVLPG M |
no |
no |
privileged, implemented badly in Intel P5 and P54 |
yes |
INVD |
no |
no |
privileged, does not write back cache contents |
yes |
WBINVD |
yes |
yes |
privileged |
no |
LMSW Ew |
yes |
no |
privileged |
yes |
MOV CR0,Rd |
yes |
yes |
privileged |
yes |
MOV CR2,Rd |
no |
no |
privileged |
yes |
MOV CR3,Rd |
no |
no |
privileged |
yes |
MOV CR4,Rd |
no |
no |
privileged |
yes |
MOV DR0..7,Rd |
yes |
yes |
privileged |
yes |
WRMSR |
n/a |
yes |
privileged |
yes |
SFENCE |
n/a |
yes |
non-privileged, but requires SSE |
yes |
MFENCE |
n/a |
yes |
non-privileged, but requires SSE2 |
yes |
LFENCE |
n/a |
yes |
non-privileged, but requires SSE2 |
no |
exceptions #4 |
yes |
no |
incl. INT Ib, INT1, INT3, INTO (taken), BOUND (taken) |
no |
interrupts #4 |
yes |
no |
INTR, NMI, SMI, INIT |
no |
branches |
yes |
no |
CALL Ap/Ep/Ev/Jv, RET, RET Iw, RETF, RETF Iw
JMP Ap/Ep/Ev/Jv/Jb, Jcc Jb/Jv (taken), JCXZ
LOOP, LOOPE, LOOPNE
|
no |
segment loads |
no |
no |
LDS/LES/LFS/LGS/LSS Gv,MP
POP DS/ES/FS/GS/SS
MOV Sw,Ew
|
notes |
description |
#1 |
Only the documented instructions and events are guaranteed to be serializing on future IA-32 processors. |
#2 |
Serializing instructions and events were defined and documented starting with Intel's P5-core processors. |
#3 |
To ensure backward compatibility it is not recommended to use these. (This depends on #1 and #2.) |
#4 |
The nature of the IA-32 architecture implies that these instructions and events are serializing. |
TLB invalidation |
- writes to CR3 #1
- changes to CR3 during a task switch #1
- changes to CR0.PE
- changes to CR0.PG #2
- changes to CR4.PSE (if PSE is supported) #2
- changes to CR4.PGE (if PGE is supported)
- changes to CR4.PAE (if PAE is supported)
- INVLPG M instruction
- RSM instruction
- writes to MTRRs (if MTRRs are supported)
- writes to PAT MSR (if PAT is supported)
|
notes |
description |
#1 |
global entries remain if PGE is supported |
#2 |
not on Intel P5-core processors |
|
PDPTE-to-PDPTR reloading |
- writes to CR3 #1
- changes to CR3 during a task switch #1, #2
- a 0-to-1 change of CR0.PG while CR4.PAE=1 #3
- a 0-to-1 change of CR4.PAE while CR0.PG=1 #3
- changes to CR4.PSE (if PSE is supported) #4
- changes to CR4.PGE (if PGE is supported) #4
- RSM instruction #5
|
notes |
description |
#1 |
while CR0.PG=1 and CR4.PAE=1 |
#2 |
Intel P4-core processors always reload |
#3 |
a 1-to-0 change should set the PDPTRs to zero |
#4 |
unnecessary, but done by Intel processors |
#5 |
SMI should save the PDPTRs in the SSM,
and then set them to zero (P6 doesn't, but P4 does)
|
|
store buffer draining |
- processor exceptions and external interrupts
- serializing instructions (see above)
- I/O instructions (IN, (REP) INS, OUT, (REP) OUTS)
- LOCKed operations (explicit and implicit)
- SFENCE instruction (if SSE is supported)
- MFENCE instruction (if SSE2 is supported)
|
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