IA-32 architecture
Centaur PeMo events




note: The following events can be counted on the Centaur WinChip processor.

#xxxxxxxxb #xx description
00000000b 00h internal clocks
00000001b 01h valid cycles reaching writebacks
00000010b 02h instructions
03..70 unknown
? 71 data read cache misses
72..73 unknown
? 74 data write cache misses
75..98 unknown
? 99 instruction fetch cache misses
99+..FFh unknown



note: The following events can be counted on the Centaur WinChip2 processor.

#xxxxxxxxb #xx description
00000000b 00h data reads
00000001b 01h data writes
00000010b 02h data TLB misses
00000011b 03h data read misses
00000100b 04h data write misses
00000101b 05h unknown
00000110b 06h data cache lines written back
00000111b 07h unknown
00001000b 08h data cache snoop hits
00001001b 09h PUSH/PUSH POP/POP pairings #1
00001010b 0Ah unknown
00001011b 0Bh misaligned data memory references
00001100b 0Ch code reads
00001101b 0Dh code TLB misses
00001110b 0Eh code cache misses
00001111b 0Fh unknown
00010000b 10h unknown
00010001b 11h unknown
00010010b 12h unknown
00010011b 13h BHT hits
00010100b 14h BHT candidates #1
00010101b 15h unknown
00010110b 16h instructions executed
00010111b 17h instructions executed in 2nd pipeline
00011000b 18h clocks while bus cycle in progress (bus utilization)
00011001b 19h unknown
00011010b 1Ah unknown
00011011b 1Bh unknown
00011100b 1Ch unknown
00011101b 1Dh I/O read or write cycles
00011110b 1Eh unknown
00011111b 1Fh unknown
00100000b 20h unknown
00100001b 21h unknown
00100010b 22h unknown
00100011b 23h unknown
00100100b 24h unknown
00100101b 25h unknown
00100110b 26h unknown
00100111b 27h unknown
00101000b 28h data reads or data writes
00101001b 29h unknown
00101010b 2Ah unknown
00101011b 2Bh MMX instructions in 1st pipeline (EC0)
MMX instructions in 2nd pipeline (EC1)
00101100b 2Ch unknown
00101101b 2Dh unknown
00101110b 2Eh unknown
00101111b 2Fh unknown
00110000b 30h unknown
00110001b 31h unknown
00110010b 32h unknown
00110011b 33h unknown
00110100b 34h unknown
00110101b 35h unknown
00110110b 36h unknown
00110111b 37h returns predicted incorrectly (EC0)
returns predicted correctly (EC1)
00111000b 38h unknown
001110001b 39h unknown
00111010b 3Axh unknown
00111011b 3Bh unknown
00111100b 3Ch unknown
00111101b 3Dh unknown
00111110b 3Eh unknown
00111110b 3Fh internal clocks (default for CTR0) #1
63..FFh unknown
note #1 These events are not Pentium-compatible.



note: The following events can be counted on the Centaur VIA Cyrix III processor.

counter event description
0 #1 0079h internal clocks
1 0079h internal clocks
00C0h instructions executed
01C0h instructions executed including string iterations
note #1 The event for counter 0 can not be changed.
The counter is always aliased to the lowest 40 bits of the TSC.



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