IA-32 architecture
segment registers
CS, SS, DS, ES, FS, GS
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
internal descriptor cache
CS for a segment or a
selector
32bit
base
32bit
limit
access
rights
SS for a segment or a
selector
32bit
base
32bit
limit
access
rights
DS for a segment or a
selector
32bit
base
32bit
limit
access
rights
ES for a segment or a
selector
32bit
base
32bit
limit
access
rights
FS for a segment or a
selector
32bit
base
32bit
limit
access
rights
GS for a segment or a
selector
32bit
base
32bit
limit
access
rights