IA-32 architecture 3DNow! opcodes
The PREFETCHx instruction is using the reg field of the mod R/M byte to
determine the desired prefetch type (x).
0Fh xxh |
xDh |
xEh |
xFh |
0xh |
PREFETCHx M |
FEMMS |
refer to table below |
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opcode |
PREFETCHx instruction |
0Fh,0Dh,xx000xxxb |
PREFETCH line into E state |
0Fh,0Dh,xx001xxxb |
PREFETCHW line into M state |
0Fh,0Dh,xx002xxxb |
reserved, alias to PREFETCH |
0Fh,0Dh,xx003xxxb |
reserved, alias to PREFETCH |
0Fh,0Dh,xx004xxxb |
reserved, alias to PREFETCH |
0Fh,0Dh,xx005xxxb |
reserved, alias to PREFETCH |
0Fh,0Dh,xx006xxxb |
reserved, alias to PREFETCH |
0Fh,0Dh,xx007xxxb |
reserved, alias to PREFETCH |
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The 3DNow! instruction encoding differs from the regular instruction encoding,
in that the mod R/M (and SIB) byte as well as an optional displacement follow
directly after the two 0Fh prefix bytes. The byte selecting the instruction
itself is appended as the last byte.
0Fh 0Fh ... xxh |
x0h |
x1h |
x2h |
x3h |
x4h |
x5h |
x6h |
x7h |
0xh |
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1xh |
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2xh |
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3xh |
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4xh |
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5xh |
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6xh |
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7xh |
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8xh |
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9xh |
PFCMPGE Pq,Qq |
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PFMIN Pq,Qq |
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PFRCP Pq,Qq |
PFRSQRT Pq,Qq |
Axh |
PFCMPGT Pq,Qq |
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PFMAX Pq,Qq |
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PFRCPIT1 Pq,Qq |
PFRSQIT1 Pq,Qq |
Bxh |
PFCMPEQ Pq,Qq |
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PFMUL Pq,Qq |
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PFRCPIT2 Pq,Qq |
PMULHRW Pq,Qq |
Cxh |
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Dxh |
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Exh |
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Fxh |
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0Fh 0Fh ... xxh |
x8h |
x9h |
xAh |
xBh |
xCh |
xDh |
xEh |
xFh |
0xh |
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PI2FW* Pq,Qq |
PI2FD Pq,Qq |
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1xh |
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PF2IW* Pq,Qq |
PF2ID Pq,Qq |
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2xh |
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3xh |
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4xh |
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5xh |
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6xh |
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7xh |
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8xh |
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PFNACC* Pq,Qq |
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PFPNACC* Pq,Qq |
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9xh |
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PFSUB Pq,Qq |
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PFADD Pq,Qq |
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Axh |
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PFSUBR Pq,Qq |
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PFACC Pq,Qq |
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Bxh |
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PSWAPD* Pq,Qq |
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PAVGUSB Pq,Qq |
Cxh |
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Dxh |
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Exh |
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Fxh |
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note: The opcodes marked with * are enhanced 3DNow! opcodes.
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