IA-32 architecture
PeMo control




 
name
 
Intel P5-core CESR and Cyrix M2 CESR
(Performance Monitoring counter Control & Event Select Register)
bit 63..32 31..27 26 25 24..22 21..16 15..11 10 9 8..6 5..0
name res. reserved ES1 PC1 CC1 ES1 reserved ES0 PC0 CC0 ES0

 
name
 
Centaur WinChip CESR
(Performance Monitoring counter Control & Event Select Register)
bit 63..32 31..24 23..16 15..8 7..0
name res. reserved ES1 reserved ES0

name description states
PC1/0 PM1/0 pin control 1=pin indicates counter overflows 0=pin indicates counter increments
CC1/0 counter #0/1 control 000b=counter disabled
001b=count events in CPL=0..2
010b=count events in CPL=3
011b=count events in CPL=all
100b=counter disabled
101b=count clocks in CPL=0..2
110b=count clocks in CPL=3
111b=count clocks in CPL=all
ES1/0 event #0/1 select event # (00..3Fh on Intel P5-core, 00..7Fh on Cyrix M2, 00..FFh on Centaur WinChip
note Bit 26 and bit 10 are only defined for Cyrix M2 processors.



 
name
 
Intel P6-core or VIA Cyrix III CESR #0/1 and AMD K7 PerfEvSel Register #0..#3
(Performance Monitoring counter Control & Event Select Register #0/1)
bit 63..32 31..24 23 22 21 20 19 18 17 16 15..8 7..0
name res. MASK INV EN r. INT PC E OS US UNIT EVENT (or ES)

name description states
MASK increment limit limit 00..FFh (counter will be incremented if this limit was reached or exceeded) #1
INV invert MASK 1=increment if <=MASK increments #1 0=increment if >=MASK increments #1
EN enable counter #2 1=both counters are enabled 0=both counters are disabled
INT enable interrupt #3 1=overflow causes APIC interrupt 0=overflow doesn't cause APIC interrupt
PC PM1/0 pin control 1=pin indicates counter overflows 0=pin indicates counter increments
E edge detect 1=count clocks 0=count events
OS count OS 1=enable counting for CPL=0 0=disable counting for CPL=0
US count user 1=enable counting for CPL=1..3 0=disable counting for CPL=1..3
UNIT unit mask select unit mask # (see notes for P6 and K7)
ES event select event # (00..FFh for P6, K7, and VIA Cyrix III)
notes description
#1 This allows counting multiple events ("increment if at least xxh/cycle" or "increment if less than xxh/cycle").
#2 This bit is present in CESR#0 only. (Disable a single counter by selecting OS=0 and US=0.)
#3 A local APIC interrupt will be generated.



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