IA-32 architecture debug registers
debug registers DR0..7 |
reg. |
3 1 |
3 0 |
2 9 |
2 8 |
2 7 |
2 6 |
2 5 |
2 4 |
2 3 |
2 2 |
2 1 |
2 0 |
1 9 |
1 8 |
1 7 |
1 6 |
1 5 |
1 4 |
1 3 |
1 2 |
1 1 |
1 0 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
DR0 |
breakpoint #0 virtual address |
DR1 |
breakpoint #1 virtual address |
DR2 |
breakpoint #2 virtual address |
DR3 |
breakpoint #3 virtual address |
DR4 |
reserved |
DR5 |
reserved |
DR6 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
B T |
B S |
B D |
S M M |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
B 3 |
B 2 |
B 1 |
B 0 |
DR7 |
LEN 3 |
R/W 3 |
LEN 2 |
R/W 2 |
LEN 1 |
R/W 1 |
LEN 0 |
R/W 0 |
T T |
T B |
G D |
I C E |
r. |
1 |
G E |
L E |
G 3 |
L 3 |
G 2 |
L 2 |
G 1 |
L 1 |
G 0 |
L 0 |
|