IA-32 architecture CPUID
Before trying to rely upon CPUID, a program must properly detect and sometimes
enable the instruction. In particular, the program must detect the presence of
a 32bit IA-32 processor, which supports the EFLAGS register. Next, if it is a
Cyrix or a NexGen processor, the CPUID instruction may have to be enabled. Then
the program must try to toggle the ID bit in the EFLAGS register, to determine
whether the instruction is supported or not. Note that the program may face one
of the early Intel P5 processors: they do neither return a vendor ID string
nor the maximum supported standard level, when level 0000_0000h is queried.
Finally, notice that some chips support a partially programmable CPUID
instruction -- thanks to those idiot programmers who hard-coded "GenuineIntel"
all over the place...
standard level 0000_0000h |
input |
EAX=0000_0000h |
get maximum supported standard level and vendor ID string |
output |
EAX=xxxx_xxxxh |
maximum supported standard level #1 |
EBX-EDX-ECX |
vendor ID string #2 |
GenuineIntel |
Intel processor |
UMC UMC UMC |
UMC processor |
AuthenticAMD |
AMD processor |
CyrixInstead |
Cyrix processor |
NexGenDriven |
NexGen processor |
CentaurHauls |
Centaur processor |
RiseRiseRise |
Rise Technology processor |
GenuineTMx86 |
Transmeta processor |
notes |
description |
#1 |
According to [1] and [2] the pre-B0 step Intel P5 processors return EAX=0000_05xxh. |
#2 |
According to [1] and [2] the pre-B0 step Intel P5 processors don't return a vendor ID string. |
standard level 0000_0001h |
input |
EAX=0000_0001h |
get processor type/family/model/stepping and feature flags |
output |
EAX=xxxx_xxxxh |
processor type/family/model/stepping |
extended family |
The extended processor family is encoded in bits 27..20. |
|
00h |
Intel P4 |
01h |
Intel McKinley (IA-64) |
extended model |
The extended processor model is encoded in bits 19..16. |
type |
The processor type is encoded in bit 13 and bit 12. |
|
11b |
reserved |
10b |
secondary processor (for MP) |
01b |
Overdrive processor |
00b |
primary processor |
family |
The family is encoded in bits 11..8. |
|
4 |
most 80486s
AMD 5x86
Cyrix 5x86
|
5 |
Intel P5, P54C, P55C, P24T
NexGen Nx586
Cyrix M1
AMD K5, K6
Centaur C6, C2, C3
Rise mP6
Transmeta Crusoe TM3x00 and TM5x00
|
6 |
Intel P6, P2, P3
AMD K7
Cyrix M2, VIA Cyrix III
|
7 |
Intel Merced (IA-64)
|
F |
refer to extended family
|
model |
The model is encoded in bits 7..4. |
Intel |
F |
refer to extended model |
Intel 80486 |
0 |
i80486DX-25/33 |
1 |
i80486DX-50 |
2 |
i80486SX |
3 |
i80486DX2 |
4 |
i80486SL |
5 |
i80486SX2 |
7 |
i80486DX2WB |
8 |
i80486DX4 |
9 |
i80486DX4WB |
UMC 80486 |
1 |
U5D |
2 |
U5S |
AMD 80486 |
3 |
80486DX2 |
7 |
80486DX2WB |
8 |
80486DX4 |
9 |
80486DX4WB |
E |
5x86 |
F |
5x86WB |
Cyrix 5x86 |
9 |
5x86 |
Cyrix MediaGX |
4 |
GX, GXm |
Intel P5-core |
0 |
P5 A-step |
1 |
P5 |
2 |
P54C |
3 |
P24T Overdrive |
4 |
P55C |
7 |
P54C |
8 |
P55C (0.25µm) |
NexGen Nx586 |
0 |
Nx586 or Nx586FPU (only later ones) |
Cyrix M1 |
2 |
6x86 |
Cyrix M2 |
0 |
6x86MX |
VIA Cyrix III |
5 |
Cyrix M2 core |
6 |
WinChip C5A core |
7 |
WinChip C5B core (if stepping = 0..7) |
7 |
WinChip C5C core (if stepping = 8..F) |
8 |
WinChip C5C-T core (if stepping = 0..7) |
AMD K5 |
0 |
SSA5 (PR75, PR90, PR100) |
1 |
5k86 (PR120, PR133) |
2 |
5k86 (PR166) |
3 |
5k86 (PR200) |
AMD K6 |
6 |
K6 (0.30 µm) |
7 |
K6 (0.25 µm) |
8 |
K6-2 |
9 |
K6-III |
D |
K6-2+ or K6-III+ (0.18 µm) |
Centaur |
4 |
C6 |
8 |
C2 |
9 |
C3 |
Rise |
0 |
mP6 (0.25 µm) |
2 |
mP6 (0.18 µm) |
Transmeta |
4 |
Crusoe TM3x00 and TM5x00 |
Intel P6-core |
0 |
P6 A-step |
1 |
P6 |
3 |
P2 (0.28 µm) |
5 |
P2 (0.25 µm) |
6 |
P2 with on-die L2 cache |
7 |
P3 (0.25 µm) |
8 |
P3 (0.18 µm)
with 256 KB on-die L2 cache
|
A |
P3 (0.18 µm)
with 1 or 2 MB on-die L2 cache
|
B |
P3 (0.13 µm)
with 256 or 512 KB on-die L2 cache
|
AMD K7 |
1 |
Athlon (0.25 µm) |
2 |
Athlon (0.18 µm) |
3 |
Duron (SF core) |
4 |
Athlon (TB core) |
6 |
Athlon (PM core) |
7 |
Duron (MG core) |
8 |
Athlon (TH core) |
Intel P4-core |
0 |
P4 (0.18 µm) |
1 |
P4 (0.18 µm) |
2 |
P4 (0.13 µm) |
stepping |
The stepping is encoded in bits 3..0. |
The stepping values are processor-specific. |
EBX=aall_ccbbh |
brand ID |
The brand ID is encoded in bits 7..0. |
00h |
not supported |
01h |
0.18 µm Intel Celeron |
02h |
0.18 µm Intel Pentium III |
03h |
0.18 µm Intel Pentium III Xeon |
03h |
0.13 µm Intel Celeron |
04h |
0.13 µm Intel Pentium III |
07h |
0.13 µm Intel Celeron mobile |
06h |
0.13 µm Intel Pentium III mobile |
0Ah |
0.18 µm Intel Celeron 4 |
08h |
0.18 µm Intel Pentium 4 |
09h |
0.13 µm Intel Pentium 4 |
0Eh |
0.18 µm Intel Pentium 4 Xeon |
0Bh |
0.18 µm Intel Pentium 4 Xeon MP |
0Bh |
0.13 µm Intel Pentium 4 Xeon |
0Ch |
0.13 µm Intel Pentium 4 Xeon MP |
08h |
0.13 µm Intel Celeron 4 mobile |
0Eh |
0.13 µm Intel Pentium 4 mobile (production) |
0Fh |
0.13 µm Intel Pentium 4 mobile (samples) |
CLFLUSH |
The CLFLUSH (8-byte) chunk count is encoded in bits 15..8. |
CPU count |
The logical processor count is encoded in bits 23..16. |
APIC ID |
The (fixed) default APIC ID is encoded in bits 31..24. |
EDX=xxxx_xxxxh |
feature flags |
description |
bit 31 (PBE) |
Pending Break Event, STPCLK, FERR# |
bit 30 (IA-64) |
IA-64, JMPE Jv, JMPE Ev |
bit 29 (TM) |
THERM_INTERRUPT, THERM_STATUS, and MISC_ENABLE MSRs
xAPIC thermal LVT entry
|
bit 28 (HTT) |
Hyper-Threading Technology, PAUSE |
bit 27 (SS) |
selfsnoop |
bit 26 (SSE2) |
SSE2, MXCSR, CR4.OSXMMEXCPT, #XF |
bit 25 (SSE) |
SSE, MXCSR, CR4.OSXMMEXCPT, #XF |
bit 24 (FXSR) |
FXSAVE/FXRSTOR, CR4.OSFXSR |
bit 23 (MMX) |
MMX |
bit 22 (ACPI) |
THERM_CONTROL MSR |
bit 21 (DTES) |
Debug Trace and EMON Store MSRs |
bit 20 |
reserved |
bit 19 (CLFL) |
CLFLUSH |
bit 18 (PSN) |
PSN (see standard level 0000_0003h), PSN_DISABLE MSR #1 |
bit 17 (PSE36) |
4 MB PDE bits 16..13, CR4.PSE |
bit 16 (PAT) |
PAT MSR, PDE/PTE.PAT |
bit 15 (CMOV) |
CMOVcc, if FPU=1 then also FCMOVcc/F(U)COMI(P) |
bit 14 (MCA) |
MCG_*/MCn_* MSRs, CR4.MCE, #MC |
bit 13 (PGE) |
PDE/PTE.G, CR4.PGE |
bit 12 (MTRR) |
MTRR* MSRs |
bit 11 (SEP) |
SYSENTER/SYSEXIT, SEP_* MSRs #2 |
bit 10 |
reserved |
bit 9 (APIC) |
APIC #3, #4 |
bit 8 (CX8) |
CMPXCHG8B #5 |
bit 7 (MCE) |
MCAR/MCTR MSRs, CR4.MCE, #MC |
bit 6 (PAE) |
64bit PDPTE/PDE/PTEs, CR4.PAE |
bit 5 (MSR) |
MSRs, RDMSR/WRMSR |
bit 4 (TSC) |
TSC, RDTSC, CR4.TSD (doesn't imply MSR=1) |
bit 3 (PSE) |
PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) |
bit 2 (DE) |
CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 |
bit 1 (VME) |
CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB |
bit 0 (FPU) |
FPU |
notes |
description |
#1 |
If the PSN has been disabled, then the PSN feature flag will read as 0. In
addition the value for the maximum supported standard level (reported by
standard level 0000_0000h, register EAX) will be lower.
|
#2 |
The Intel P6 processor does not support SEP, but falsely reports it. |
#3 |
If the APIC has been disabled, then the APIC feature flag will read as 0. |
#4 |
Early AMD K5 processors (SSA5) falsely used this bit to report PGE support. |
#5 |
Some processors do support CMPXCHG8B, but don't report it by default. This is due to a Windows NT bug. |
standard level 0000_0002h |
input |
EAX=0000_0002h |
get processor configuration descriptors |
output |
AL |
number of times this level must be queried to obtain all configuration descriptors #1 |
EAX.15..8 EAX.23..16 EAX.31..24
EBX.0..7 EBX.15..8 EBX.23..16 EBX.31..24
ECX.0..7 ECX.15..8 ECX.23..16 ECX.31..24
EDX.0..7 EDX.15..8 EDX.23..16 EDX.31..24
|
configuration descriptors #2 |
value |
description |
00h |
null descriptor (=unused descriptor) |
01h |
code TLB, 4K pages, 4 ways, 32 entries |
02h |
code TLB, 4M pages, fully, 2 entries |
03h |
data TLB, 4K pages, 4 ways, 64 entries |
04h |
data TLB, 4M pages, 4 ways, 8 entries |
06h |
code L1 cache, 8 KB, 4 ways, 32 byte lines |
08h |
code L1 cache, 16 KB, 4 ways, 32 byte lines |
0Ah |
data L1 cache, 8 KB, 2 ways, 32 byte lines |
0Ch |
data L1 cache, 16 KB, 4 ways, 32 byte lines |
10h |
data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) |
15h |
code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) |
1Ah |
code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64) |
22h |
code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, sectored |
23h |
code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, sectored |
25h |
code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, sectored |
29h |
code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, sectored |
39h |
code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored |
3Ch |
code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored |
40h |
no integrated L2 cache (P6 core) or L3 cache (P4 core) |
41h |
code and data L2 cache, 128 KB, 4 ways, 32 byte lines |
42h |
code and data L2 cache, 256 KB, 4 ways, 32 byte lines |
43h |
code and data L2 cache, 512 KB, 4 ways, 32 byte lines |
44h |
code and data L2 cache, 1024 KB, 4 ways, 32 byte lines |
45h |
code and data L2 cache, 2048 KB, 4 ways, 32 byte lines |
50h |
code TLB, 4K/4M/2M pages, fully, 64 entries |
51h |
code TLB, 4K/4M/2M pages, fully, 128 entries |
52h |
code TLB, 4K/4M/2M pages, fully, 256 entries |
5Bh |
data TLB, 4K/4M pages, fully, 64 entries |
5Ch |
data TLB, 4K/4M pages, fully, 128 entries |
5Dh |
data TLB, 4K/4M pages, fully, 256 entries |
66h |
data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored |
67h |
data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored |
68h |
data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored |
70h |
trace L1 cache, 12 KµOPs, 8 ways |
71h |
trace L1 cache, 16 KµOPs, 8 ways |
72h |
trace L1 cache, 32 KµOPs, 8 ways |
77h |
code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64) |
79h |
code and data L2 cache, 128 KB, 8 ways, 64 byte lines, sectored |
7Ah |
code and data L2 cache, 256 KB, 8 ways, 64 byte lines, sectored |
7Bh |
code and data L2 cache, 512 KB, 8 ways, 64 byte lines, sectored |
7Ch |
code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, sectored |
7Eh |
code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sectored |
81h |
code and data L2 cache, 128 KB, 8 ways, 32 byte lines |
82h |
code and data L2 cache, 256 KB, 8 ways, 32 byte lines |
83h |
code and data L2 cache, 512 KB, 8 ways, 32 byte lines |
84h |
code and data L2 cache, 1024 KB, 8 ways, 32 byte lines |
85h |
code and data L2 cache, 2048 KB, 8 ways, 32 byte lines |
88h |
code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64) |
89h |
code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64) |
8Ah |
code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64) |
8Dh |
code and data L3 cache, 3096 KB, 12 ways, 128 byte lines (IA-64) |
90h |
code TLB, 4K...256M pages, fully, 64 entries (IA-64) |
96h |
data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64) |
9Bh |
data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64) |
value |
description |
70h |
Cyrix specific: code and data TLB, 4K pages, 4 ways, 32 entries |
74h |
Cyrix specific: ??? |
77h |
Cyrix specific: ??? |
80h |
Cyrix specific: code and data L1 cache, 16 KB, 4 ways, 16 byte lines |
82h |
Cyrix specific: ??? |
84h |
Cyrix specific: ??? |
value |
description |
others |
reserved |
example (here: P6) |
EAX=0302_0101h
EBX=0000_0000h
ECX=0000_0000h
EDX=0604_0A43h
|
Because AL is 01h, one invocation of the level is enough to obtain all the
configuration descriptors. All of them are valid because their highest bits
are 0. This P6 processor includes a 4K/M code/data TLB, an 8+8 KB code/data
L1 cache and an integrated 512 KB code and data L2 cache.
|
notes |
description |
#1 |
In a MP system special precautions must be taken when executing standard
level 0000_0002h more than once. In particular it must be ensured that the
same CPU is used during that entire process.
|
#2 |
Programs must no expect any particular order for the reported configuration descriptors. |
standard level 0000_0003h |
input |
EAX=0000_0003h |
get processor serial number #1 |
output |
EBX=xxxx_xxxxh |
processor serial number (Transmeta Crusoe processors only) |
ECX=xxxx_xxxxh |
processor serial number |
EDX=xxxx_xxxxh |
processor serial number |
note |
description |
#1 |
This level is only supported and enabled if the PSN feature flag is set. The
reported processor serial number should be combined with the vendor ID string
and the processor type/family/model/stepping value, to distinguish cases in
which two processors from different vendors happen to have the same serial
number. Finally, it should be noted that most vendors can not guarantee that
their serial numbers are truely unique.
|
extended level 8000_0000h |
input |
EAX=8000_0000h |
get maximum supported extended level and vendor ID string |
output |
EAX=xxxx_xxxxh |
maximum supported extended level |
EBX-EDX-ECX |
vendor ID string |
AuthenticAMD |
AMD processor |
reserved |
Cyrix processor |
reserved |
Centaur processor |
reserved |
Intel processor |
TransmetaCPU |
Transmeta processor |
extended level 8000_0001h |
input |
EAX=8000_0001h |
get processor family/model/stepping and features flags #0 |
output |
EAX=0000_0xxxh |
processor family/model/stepping |
family |
The family is encoded in bits 11..8. |
|
5 |
AMD K5
Centaur C2
Transmeta Crusoe TM3x00 and TM5x00
|
6 |
AMD K6
VIA Cyrix III
|
7 |
AMD K7 |
model |
The model is encoded in bits 7..4. |
AMD K5 |
1 |
5k86 (PR120 or PR133) |
2 |
5k86 (PR166) |
3 |
5k86 (PR200) |
AMD K6 |
6 |
K6 (0.30 µm) |
7 |
K6 (0.25 µm) |
8 |
K6-2 |
9 |
K6-III |
D |
K6-2+ or K6-III+ (0.18 µm) |
AMD K7 |
1 |
Athlon (0.25 µm) |
2 |
Athlon (0.18 µm) |
3 |
Duron (SF core) |
4 |
Athlon (TB core) |
6 |
Athlon (PM core) |
7 |
Duron (MG core) |
8 |
Athlon (TH core) |
Centaur |
8 |
C2 |
9 |
C3 |
VIA Cyrix III |
5 |
Cyrix M2 core |
6 |
WinChip C5A core |
7 |
WinChip C5B core (if stepping = 0..7) |
7 |
WinChip C5C core (if stepping = 8..F) |
8 |
WinChip C5C-T core (if stepping = 0..7) |
Transmeta |
4 |
Crusoe TM3x00 and TM5x00 |
stepping |
The stepping is encoded in bits 3..0. |
The stepping values are processor-specific. |
EDX=xxxx_xxxxh |
feature flags |
description of indicated feature |
bit 31 (3DNow!) |
3DNow! |
bit 30 (3DNow!+) |
extended 3DNow! |
bit 29 (LM) |
AA-64, Long Mode |
bit 28 |
reserved |
bits 27..25 |
reserved |
bit 24 (MMX+)
bit 24 (FXSR)
|
Cyrix specific: extended MMX
AMD K7: FXSAVE/FXRSTOR, CR4.OSFXSR
|
bit 23 (MMX) |
MMX |
bit 22 (MMX+) |
AMD specific: MMX-SSE and SSE-MEM |
bit 21 |
reserved |
bit 20 (NX) |
EFER.NXE, P?E.NX, #PF(1xxxx) |
bit 19 (MP) |
MP-capable #3 |
bit 18 |
reserved |
bit 17 (PSE36) |
4 MB PDE bits 16..13, CR4.PSE |
bit 16 (FCMOV)
bit 16 (PAT)
|
FCMOVcc/F(U)COMI(P) (implies FPU=1)
AMD K7: PAT MSR, PDE/PTE.PAT
|
bit 15 (CMOV) |
CMOVcc |
bit 14 (MCA) |
MCG_*/MCn_* MSRs, CR4.MCE, #MC |
bit 13 (PGE) |
PDE/PTE.G, CR4.PGE |
bit 12 (MTRR) |
MTRR* MSRs |
bit 11 (SEP) |
SYSCALL/SYSRET, EFER/STAR MSRs #1 |
bit 10 |
reserved #1 |
bit 9 (APIC) |
APIC #2 |
bit 8 (CX8) |
CMPXCHG8B |
bit 7 (MCE) |
MCAR/MCTR MSRs, CR4.MCE, #MC |
bit 6 (PAE) |
64bit PDPTE/PDE/PTEs, CR4.PAE |
bit 5 (MSR) |
MSRs, RDMSR/WRMSR |
bit 4 (TSC) |
TSC, RDTSC, CR4.TSD (doesn't imply MSR=1) |
bit 3 (PSE) |
PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) |
bit 2 (DE) |
CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 |
bit 1 (VME) |
CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB |
bit 0 (FPU) |
FPU |
note |
description |
#0 |
Intel processors don't support this function; they return zero in EAX, EBX, ECX, and EDX. |
#1 |
The AMD K6 processor, model 6, uses bit 10 to indicate SEP. Beginning with model 7, bit 11 is used instead. |
#2 |
If the APIC has been disabled, then the APIC feature flag will read as 0. |
#3 |
AMD K7 processors prior to CPUID=0662h may report 0 even if they are MP-capable. |
extended levels 8000_0002h, 8000_0003h, and 8000_0004h |
input |
EAX=8000_0002h |
get processor name string (part 1) |
EAX=8000_0003h |
get processor name string (part 2) |
EAX=8000_0004h |
get processor name string (part 3) |
output |
EAX
EBX
ECX
EDX
|
processor name string #1 |
AMD K5 |
AMD-K5(tm) Processor |
AMD K6 |
AMD-K6tm w/ multimedia extensions |
AMD K6-2 |
AMD-K6(tm) 3D processor
AMD-K6(tm)-2 Processor
|
AMD K6-III |
AMD-K6(tm) 3D+ Processor
AMD-K6(tm)-III Processor
|
AMD K6-2+ |
AMD-K6(tm)-III Processor (?) |
AMD K6-III+ |
AMD-K6(tm)-III Processor (?) |
AMD K7 |
AMD-K7(tm) Processor (model 1)
AMD Athlon(tm) Processor (model 2)
AMD Athlon(tm) Processor (models 3/4, 6/7, and 8 -- programmable)
|
Centaur C2 #2 |
IDT WinChip 2
IDT WinChip 2-3D
|
VIA Cyrix III |
CYRIX III(tm) (?)
VIA Samuel (?)
VIA Ezra (?)
|
Intel P4 |
Intel(R) Pentium(R) 4 CPU xxxxMHz (right-justified, leading whitespaces) |
Transmeta |
Transmeta(tm) Crusoe(tm) Processor TMxxxx |
notes |
description |
#1 |
Unused characters at the end of the string are filled with 00h. |
#2 |
The string depends on whether 3DNow! is disabled or enabled. |
extended level 8000_0005h |
input |
EAX=8000_0005h |
get L1 cache and TLB configuration descriptors #1 |
output |
EAX |
4/2 MB L1 TLB configuration descriptor |
bits |
description |
31..24 |
data TLB associativity (FFh=full) |
23..16 |
data TLB entries |
15..8 |
code TLB associativity (FFh=full) |
7..0 |
code TLB entries |
EBX |
4 KB L1 TLB configuration descriptor #2 |
bits |
description |
31..24 |
data TLB associativity (FFh=full) |
23..16 |
data TLB entries |
15..8 |
code TLB associativity (FFh=full) |
7..0 |
code TLB entries |
ECX |
data L1 cache configuration descriptor |
bits |
description |
31..24 |
data L1 cache size in KBs |
23..16 |
data L1 cache associativity (FFh=full) |
15..8 |
data L1 cache lines per tag |
7..0 |
data L1 cache line size in bytes |
EDX |
code L1 cache configuration descriptor |
bits |
description |
31..24 |
code L1 cache size in KBs |
23..16 |
code L1 cache associativity (FFh=full) |
15..8 |
code L1 cache lines per tag |
7..0 |
code L1 cache line size in bytes |
notes |
description |
#1 |
Cyrix processors return CPUID level 0000_0002h-like descriptors instead. |
#2 |
While Transmeta Crusoe processors have 256 entries, the CPUID definition constrains them to reporting only 255.
For compatibility reasons they report their unified TLB twice: once for the code TLB, and once for the data TLB.
|
extended level 8000_0006h |
input |
EAX=8000_0006h |
get L2 cache configuration descriptors |
output |
EAX |
4/2 MB L2 TLB configuration descriptor #1 |
bits |
description |
31..28 |
data TLB associativity #2 |
27..16 |
data TLB entries |
15..12 |
code TLB associativity #2 |
11..0 |
code TLB entries |
EBX |
4 KB L2 TLB configuration descriptor #1 |
bits |
description |
31..28 |
data TLB associativity #2 |
27..16 |
data TLB entries |
15..12 |
code TLB associativity #2 |
11..0 |
code TLB entries |
ECX |
unified L2 cache configuration descriptor #3 |
bits |
description |
31..16 #5 |
unified L2 cache size in KBs #4 |
15..12 #5 |
unified L2 cache associativity #2 |
11..8 #5 |
unified L2 cache lines per tag |
7..0 |
unified L2 cache line size in bytes |
note |
description |
#1 |
A unified L2 TLB is indicated by a value of 0000h in the upper 16 bits. |
#2 |
0000b=L2 off, 0001b=direct mapped, 0010b=2-way, 0100b=4-way, 0110b=8-way, 1000b=16-way, 1111b=full |
#3 |
The AMD K7 processor's L2 cache must be configured prior to relying upon this information. |
#4 |
AMD K7 processors with CPUID=0630h (Duron) falsely report 1 KB instead of 64 KB. |
#5 |
VIA Cyrix III processors with CPUID=0670..068Fh (C5B/C5C) falsely use bits 31..24, 23..16, and 15..8 instead. |
extended level 8000_0007h |
input |
EAX=8000_0007h |
get enhanced power management (EPM) information |
output |
EDX |
EPM flags |
bits |
description |
31..3 |
reserved |
2 (VID) |
voltage ID control supported |
1 (FID) |
frequency ID control supported |
0 |
temperature sensing diode supported |
extended level 8000_0008h |
input |
EAX=8000_0008h |
get address size information |
output |
EAX |
address size information |
bits |
description |
31..16 |
reserved |
15..8 |
virtual address bits |
7..0 |
physical address bits |
Transmeta level 8086_0000h |
input |
EAX=8086_0000h |
get maximum supported level and vendor ID string |
output |
EAX=xxxx_xxxxh |
maximum supported level |
EBX-EDX-ECX |
vendor ID string |
TransmetaCPU |
Transmeta processor |
Transmeta level 8086_0001h |
input |
EAX=8086_0001h |
get processor information |
output |
EAX=0000_0xxxh |
processor family/model/stepping |
family |
The family is encoded in bits 11..8. |
|
5 |
Transmeta Crusoe TM3x00 and TM5x00
|
model |
The model is encoded in bits 7..4. |
Transmeta |
4 |
Crusoe TM3x00 and TM5x00 |
stepping |
The stepping is encoded in bits 3..0. |
The stepping values are processor-specific. |
EBX=aabb_ccddh |
hardware revision (a.b-c.d) |
ECX=xxxx_xxxxh |
nominal core clock frequency (MHz) |
EDX=xxxx_xxxxh |
feature flags |
description of indicated feature |
bits 31..4 |
reserved |
bit 3 (LRTI) |
LongRun Table Interface |
bit 2 (???) |
unknown |
bit 1 (LR) |
LongRun |
bit 0 (BAD) |
recovery CMS active (due to a failed upgrade) |
Transmeta level 8086_0002h |
input |
EAX=8086_0002h |
get processor information |
output |
EBX |
aabb_ccddh |
software revision, part 1/2 (a.b.c-d-x) |
ECX |
xxxx_xxxxh |
software revision, part 2/2 (a.b.c-d-x) |
Transmeta levels 8086_0003h, 8086_0004h, 8086_0005h, and 8086_0006h |
input |
EAX=8086_0003h |
get information string (part 1) |
EAX=8086_0004h |
get information string (part 2) |
EAX=8086_0005h |
get information string (part 3) |
EAX=8086_0006h |
get information string (part 4) |
output |
EAX-EBX-ECX-EDX
|
information string #1 |
Transmeta |
20000805 23:30 official release 4.1.4#2 (example) |
notes |
description |
#1 |
Unused characters at the end of the string are filled with 00h. |
Transmeta level 8086_0007h |
input |
EAX=8086_0007h |
get processor information |
output |
EAX |
xxxx_xxxxh |
current core clock frequency (MHz) |
EBX |
xxxx_xxxxh |
current core clock voltage (mV) |
ECX |
xxxx_xxxxh |
current (LongRun) performance level (0..100%) |
EDX |
xxxx_xxxxh |
unknown |
mystery level 8FFF_FFFEh |
input |
EAX=8FFF_FFFEh |
unknown #1 |
output |
EAX |
0049_4544h |
DEI (according to one source: Divide Et Impera = Divide And Rule) |
EBX |
0000_0000h |
reserved |
ECX |
0000_0000h |
reserved |
EDX |
0000_0000h |
reserved |
note |
description |
#1 |
This level is only supported by the AMD K6 processor family. |
mystery level 8FFF_FFFFh |
input |
EAX=8FFF_FFFFh |
unknown #1 |
output |
EAX
EBX
ECX
EDX
|
string |
NexGenerationAMD |
note |
description |
#1 |
This level is only supported by the AMD K6 processor family. |
all other levels |
input |
EAX=xxxx_xxxxh |
desired CPUID level |
output |
EAX=xxxx_xxxxh
EBX=xxxx_xxxxh
ECX=xxxx_xxxxh
EDX=xxxx_xxxxh
|
undefined |
|