IA-32 architecture
Intel P5-core PeMo events




#xxxxxxb #xxh description occurence/duration
000000b 00h data reads occurence
000001b 01h data writes occurence
000010b 02h data TLB misses occurence
000011b 03h data read misses occurence
000100b 04h data write misses occurence
000101b 05h writes (hits) to M or E state lines occurence
000110b 06h data cache lines written back occurence
000111b 07h data cache snoops occurence
001000b 08h data cache snoop hits occurence
001001b 09h memory accesses in both pipes occurence
001010b 0Ah bank conflicts occurence
001011b 0Bh misaligned data memory references occurence
001100b 0Ch code reads occurence
001101b 0Dh code TLB misses occurence
001110b 0Eh code cache misses occurence
001111b 0Fh any segment register loaded occurence
010000b 10h segment descriptor cache accesses occurence
010001b 11h segment descriptor cache hits occurence
010010b 12h branches occurence
010011b 13h BTB hits occurence
010100b 14h taken branches or BTB hits occurence
010101b 15h pipeline flushes occurence
010110b 16h instructions executed in both pipes occurence
010111b 17h instructions executed in the v-pipe occurence
011000b 18h clocks while bus cycle in progress (bus utilization) duration
011001b 19h pipe stalled by full write buffers (writes backup) duration
011010b 1Ah pipe stalled by waiting for data memory reads duration
011011b 1Bh pipe stalled by writes to M or E lines duration
011100b 1Ch locked bus cycles occurence
011101b 1Dh I/O read or write cycles occurence
011110b 1Eh non-cacheable memory references occurence
011111b 1Fh pipeline stalled by address generation interlock duration
100000b 20h source destination conflicts occurence
100001b 21h reserved
100010b 22h floating-point operations occurence
100011b 23h breakpoint matches on DR0 register occurence
100100b 24h breakpoint matches on DR1 register occurence
100101b 25h breakpoint matches on DR2 register occurence
100110b 26h breakpoint matches on DR3 register occurence
100111b 27h hardware interrupts occurence
101000b 28h data reads or data writes occurence
101001b 29h data read misses or data write misses occurence



note: The following events are only available on Intel P55 processors.

#xxxxxxb #xxh description occurence/duration
101010b 2Ah bus ownership latency duration
bus ownership transfers occurence
101011b 2Bh MMX instructions executed in u-pipe occurence
MMX instructions executed in v-pipe occurence
101100b 2Ch cache M state line sharing occurence
cache line sharing occurence
101101b 2Dh EMMS instructions executed occurence
transition between MMX and FP instructions occurence
101110b 2Eh bus utilization due to processor activity duration
writes to non-cacheable memory occurence
101111b 2Fh saturating MMX instructions executed occurence
saturations performed occurence
110000b 30h number of cycles not in HLT state duration
number of cycles not in HLT state duration
110001b 31h MMX instruction data reads occurence
MMX instruction data read misses occurence
110010b 32h floating point stalls duration
taken branches occurence
110011b 33h D1 starvation and FIFO is empty occurence
D1 starvation and one instruction in FIFO occurence
110100b 34h MMX instruction data writes occurence
MMX instruction data write misses occurence
110101b 35h pipeline flushes due to wrong branch prediction occurence
pipeline flushes due to wrong branch prediction, but resolved in WB-stage occurence
110110b 36h misaligned data memory reference on MMX instruction occurence
pipeline stalled waiting for MMX instruction data memory read duration
110111b 37h returns, predicted incorrectly or not predicted at all occurence
returns, predicted (correctly and incorrectly) occurence
111000b 38h MMX instruction multiply unit interlock duration
MOVD/MOVQ store stall due to previous operation duration
111001b 39h returns occurence
RSB (return stack buffer) overflows occurence
111010b 3Ah BTB false entries occurence
BTB miss prediction on a not taken branch occurence
111011b 3Bh stalled due to full write buffers while executing MMX instruction duration
stall on MMX instruction write to E or M line duration
111100b 3Ch reserved
111101b 3Dh reserved
111110b 3Eh reserved
111111b 3Fh reserved
note Depending on which counter is used for the events 2A..3Fh, two different events are counted on Intel P55 processors. The first listed event is for counter #0, while the second one is for counter #1.



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