IA-32 architecture
paging




 
page size and used paging structures
 
CR0.PG CR4.PAE CR4.PSE PDE.PS physical
address
size
page size CR3
points
to
PDPT PD PT
 
0
 
x x x 32bit --- --- --- --- ---
1 0 0 x 32bit 4KB PD --- 1024
PDEs
(32bit)
1024
PTEs
(32bit)
1 0 1 0 32bit 4KB PD --- 1024
PDEs
(32bit)
1024
PTEs
(32bit)
1 0 1 1 32bit
or
36bit
4MB PD --- 1024
PDEs
(32bit)
1024
PTEs
(32bit)
1 1 x 0 36bit 4KB PDPT 4
PDPTEs
(64bit)
512
PDEs
(64bit)
512
PTEs
(64bit)
1 1 x 1 36bit 2MB PDPT 4
PDPTEs
(64bit)
512
PDEs
(64bit)
512
PTEs
(64bit)

 
virtual address translation
 
P
S
P
A
E
  3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
4
K
B
0 PDE # PTE # offset
4
M
B
PDE # offset
4
K
B
1 PDP-
TE #
PDE # PTE # offset
2
M
B
PDP-
TE #
PDE # offset



 
4KB/4MB paging structures
 
entry 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
4KB
PDE
page table base AVL G 0 D A P
C
D
P
W
T
U
/
S
W
/
R
P
4MB
PDE
page base reserved P
A
T
AVL G 1 D A P
C
D
P
W
T
U
/
S
W
/
R
P
page base (low) reserved p. b. (high)
4KB
PTE
page base AVL G P
A
T
D A P
C
D
P
W
T
U
/
S
W
/
R
P

 
4KB/2MB paging structures
 
entry 6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
PDPTE reserved page
directory
base
page directory base AVL res. P
C
D
P
W
T
res. P
4KB
PDE
reserved page
table
base
page table base AVL G 0 D A P
C
D
P
W
T
U
/
S
W
/
R
P
2MB
PDE
 
reserved
 
page
base
page base reserved P
A
T
AVL G 1 D A P
C
D
P
W
T
U
/
S
W
/
R
P
4KB
PTE
 
reserved
 
page
base
page base AVL G P
A
T
D A P
C
D
P
W
T
U
/
S
W
/
R
P



 
#PF exception error code
 
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
reserved R
S
V
U
/
S
W
/
R
P



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