IA-32 architecture interrupts
interrupts |
name |
type |
latched? |
block? |
description |
RESET |
input |
level #1 |
asynch |
no |
no |
reset the processor |
STPCLK |
input |
level |
asynch |
no |
no |
stop the processor |
SMI |
input |
edge |
asynch |
yes #2 |
yes #3 |
system management interrupt |
INIT #4 |
input |
edge |
asynch |
yes #2 |
yes #3 |
initialize the processor |
NMI #5 |
input |
edge |
asynch |
yes #2 |
yes #3 |
non-maskable interrupt |
INTR #5 |
input |
level #6 |
asynch #7 |
no #6 |
if IF=0 |
maskable interrupt |
notes |
description |
#1 |
Depending on the processor, RESET must meet a certain minimum hold time. |
#2 |
One occurence of the signal can be latched while the signal is blocked. Refer to SMM for details. |
#3 |
The signal is blocked and unblocked by various events. Refer to MSRs, SMM, and initial state for details. |
#4 |
For Intel P6-core processors, INIT is active low, ie. INIT#. |
#5 |
For Intel P6-core processors, NMI is equal to LINT1, and INTR is equal to LINT0. |
#6 |
If INTR is deasserted before the first INTA cycle completed, then the processor will not recognize it. |
#7 |
The processor must however follow the INTR-INTA-vector-INTA protocol, to determine the interrupt vector. |
interrupt suppression |
name |
suppressed by #1,#2 |
STI |
POP SS |
MOV SS,Ew |
RESET |
no |
no |
no |
STPCLK #3 |
no |
no |
no |
INIT |
yes #4 |
yes #4 |
yes #4 |
SMI |
yes #5 |
yes |
yes |
NMI |
yes #5 |
yes |
yes |
INTR |
yes |
yes |
yes |
STPCLK #3 |
yes |
yes |
yes |
notes |
description |
#1 |
A suppression of at least one instruction is guaranteed. (It may be longer.) |
#2 |
If the suppressing instruction is followed by a HLT, REP string instruction, or
a FP instruction that causes a freeze, then the suppression will end eventually, to
permit interrupt service. Also, for a stream of suppressing instructions
only the first suppression is guaranteed.
Last but not least, if the suppressing instruction is followed by a trap or a
fault, then the suppression should end, so that the first instruction of the
exception handler can be a suppressing one.
|
#3 |
If STPCLK is implemented with higher priority than INIT, then it will not be
suppressed. By contrast, if STPCLK is implemented with lower priority
than INTR, it must be suppressed, to ensure proper prioritization.
|
#4 |
INIT must be suppressed to ensure its proper prioritization versus SMI. |
#5 |
Since the INTR suppression is not preserved accross the NMI or the SMI
handler, STI must also suppress NMI or SMI.
|
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