IA-32 architecture
Intel P6-core PeMo events




event part #5 unit #6 description
00h ? ? documented as unused
01h ? ? documented as unused
02h ? ? documented as unused
03h MO store buffer blocks
04h MO store buffer drain cycles
05h MO misaligned data memory references
06h SRL segment register loads
07h MO SSE-MEM SSE prefetch/weakly ordered instructions dispatched #4
08h ? ? documented as unused
09h ? ? documented as unused
0Ah ? ? documented as unused
0Bh ? ? documented as unused
0Ch ? ? documented as unused
0Dh ? ? documented as unused
0Eh ? ? documented as unused
0Fh ? ? documented as unused
10h FPU executed computational FLOPS #1
11h FPU MC handled FP exception cases #2
12h FPU multiplies #2
13h FPU divides #2
14h FPU divider busy cycles #1
15h ? ? documented as unused
16h ? ? documented as unused
17h ? ? documented as unused
18h ? ? documented as unused
19h ? ? documented as unused
1Ah ? ? documented as unused
1Bh ? ? documented as unused
1Ch ? ? documented as unused
1Dh ? ? documented as unused
1Eh ? ? documented as unused
1Fh ? ? documented as unused
20h ? ? documented as unused
21h L2 address strobes
22h L2 data bus waiting cycles
23h L2 data bus transfer cycles
24h L2 allocated lines
25h L2 allocated modified lines
26h L2 removed lines
27h L2 removed modified lines
28h L2 MESI instruction fetches
29h L2 MESI loads
2Ah L2 MESI stores
2Bh ? ? documented as unused
2Ch ? ? documented as unused
2Dh ? ? documented as unused
2Eh L2 MESI requests
2Fh ? ? documented as unused
30h ? ? documented as unused
31h ? ? documented as unused
32h ? ? documented as unused
33h ? ? documented as unused
34h ? ? documented as unused
35h ? ? documented as unused
36h ? ? documented as unused
37h ? ? documented as unused
38h ? ? documented as unused
39h ? ? documented as unused
3Ah ? ? documented as unused
3Bh ? ? documented as unused
3Ch ? ? documented as unused
3Dh ? ? documented as unused
3Eh ? ? documented as unused
3Fh ? ? documented as unused
40h ? ? documented as unused
41h ? ? documented as unused
42h ? ? documented as unused
43h L1d memory references
44h ? ? documented as unused
45h L1d allocated lines
46h L1d allocated M state lines
47h L1d evicted M state lines
48h L1d outstanding miss cycles (weighted)
49h ? ? documented as unused
4Ah ? ? documented as unused
4Bh MO SSE-MEM SSE prefetch/weakly ordered instructions that misses all caches #4
4Ch ? ? documented as unused
4Dh ? ? documented as unused
4Eh ? ? documented as unused
4Fh ? ? documented as unused
50h ? ? documented as unused
51h ? ? documented as unused
52h ST self-modifying code occurences #3
53h ? ? documented as unused
54h ? ? documented as unused
55h ? ? documented as unused
56h ? ? documented as unused
57h ? ? documented as unused
58h ? ? documented as unused
59h ? ? documented as unused
5Ah ? ? documented as unused
5Bh ? ? documented as unused
5Ch ? ? documented as unused
5Dh ? ? documented as unused
5Eh ? ? documented as unused
5Fh ? ? documented as unused
60h EBL oustanding bus requests
61h EBL BNR driven cycles
62h EBL CPU DRDY asserted cycles
63h EBL CPU LOCK asserted cycles
64h EBL CPU receiving data cycles
65h EBL CPU burst read transactions
66h EBL CPU read for ownership transactions
67h EBL CPU write back transactions
68h EBL CPU instruction fetch transactions
69h EBL CPU invalidate transactions
6Ah EBL CPU partial write transactions
6Bh EBL CPU partial transactions
6Ch EBL CPU I/O transactions
6Dh EBL CPU deferred transactions
6Eh EBL CPU burst transactions
6Fh EBL CPU memory transactions
70h EBL CPU all transactions
71h ? ? documented as unused
72h ? ? documented as unused
73h ? ? documented as unused
74h ? ? documented as unused
75h ? ? documented as unused
76h ? ? documented as unused
77h ? ? documented as unused
78h ? ? documented as unused
79h CLK processor not halted cycles
7Ah EBL HIT driven cycles
7Bh EBL HITM driven cycles
7Ch ? ? documented as unused
7Dh ? ? documented as unused
7Eh EBL bus snoop stall cycles
7Fh ? ? documented as unused
80h IFU instruction fetches
81h IFU instruction fetch misses
82h ? ? documented as unused
83h ? ? documented as unused
84h ? ? documented as unused
85h IFU iTLB misses
86h IFU instruction fetch stall cycles
87h IFU instruction length decoder stall cycles
88h ? ? documented as unused
89h ? ? documented as unused
8Ah ? ? documented as unused
8Bh ? ? documented as unused
8Ch ? ? documented as unused
8Dh ? ? documented as unused
8Eh ? ? documented as unused
8Fh ? ? documented as unused
90h ? ? documented as unused
91h ? ? documented as unused
92h ? ? documented as unused
93h ? ? documented as unused
94h ? ? documented as unused
95h ? ? documented as unused
96h ? ? documented as unused
97h ? ? documented as unused
98h ? ? documented as unused
99h ? ? documented as unused
9Ah ? ? documented as unused
9Bh ? ? documented as unused
9Ch ? ? documented as unused
9Dh ? ? documented as unused
9Eh ? ? documented as unused
9Fh ? ? documented as unused
A0h ? ? documented as unused
A1h ? ? documented as unused
A2h ST resource related stall cycles
A3h ? ? documented as unused
A4h ? ? documented as unused
A5h ? ? documented as unused
A6h ? ? documented as unused
A7h ? ? documented as unused
A8h ? ? documented as unused
A9h ? ? documented as unused
AAh ? ? documented as unused
ABh ? ? documented as unused
ACh ? ? documented as unused
ADh ? ? documented as unused
AEh ? ? documented as unused
AFh ? ? documented as unused
B0h MMX MMX instructions executed #3
B1h MMX saturated arithmetic instructions executed #3
B2h MMX PORT MMX uOPs executed on port #0..3 #3
B3h MMX OP MMX instructions #3
B4h ? ? documented as unused
B5h ? ? documented as unused
B6h ? ? documented as unused
B7h ? ? documented as unused
B8h ? ? documented as unused
B9h ? ? documented as unused
BAh ? ? documented as unused
BBh ? ? documented as unused
BCh ? ? documented as unused
BDh ? ? documented as unused
BEh ? ? documented as unused
BFh ? ? documented as unused
C0h IDR retired instructions
C1h FPU retired FLOPS #1
C2h IDR retired uOPs
C3h ? ? documented as unused
C4h BR retired branch instructions
C5h BR retired mispredicted branches
C6h INT disabled interrupts cycles
C7h INT disabled interrupts pending cycles
C8h INT received hardware interrupts
C9h BR retired taken branches
CAh BR retired taken mispredicted branches
CBh ? ? documented as unused
CCh MMX DIR transitions between FP and MMX states #3
CDh MMX SIMD assists (EMMS instructions executed) #3
CEh MMX MMX instructions retired #3
CFh MMX saturated arithmetic instructions retired #3
D0h IDR decoded instructions
D1h ? ? documented as unused
D2h ST partial stall cycles or events
D3h ? ? documented as unused
D4h SRL SREG segment rename stalls #3
D5h SRL SREG segment renames #3
D6h SRL retired segment renames #3
D7h ? ? documented as unused
D8h IDR SSE retired SSE instructions #4
D9h IDR SSE retired compuation SSE instructions #4
DAh ? ? documented as unused
DBh ? ? documented as unused
DCh ? ? documented as unused
DDh ? ? documented as unused
DEh ? ? documented as unused
DFh ? ? documented as unused
E0h BR decoded branch instructions
E1h ? ? documented as unused
E2h BR BTB misses
E3h ? ? documented as unused
E4h BR bogus branches
E5h ? ? documented as unused
E6h BR BACLEAR asserted
E7h ? ? documented as unused
E8h ? ? documented as unused
E9h ? ? documented as unused
EAh ? ? documented as unused
EBh ? ? documented as unused
ECh ? ? documented as unused
EDh ? ? documented as unused
EEh ? ? documented as unused
EFh ? ? documented as unused
F0h ? ? documented as unused
F1h ? ? documented as unused
F2h ? ? documented as unused
F3h ? ? documented as unused
F4h ? ? documented as unused
F5h ? ? documented as unused
F6h ? ? documented as unused
F7h ? ? documented as unused
F8h ? ? documented as unused
F9h ? ? documented as unused
FAh ? ? documented as unused
FBh ? ? documented as unused
FCh ? ? documented as unused
FDh ? ? documented as unused
FEh ? ? documented as unused
FFh ? ? documented as unused

note: The following events may exist, but haven't been confirmed yet.

event part #5 unit #6 description
? L2 ? L2 cache writes
? L2 ? L2 cache write misses
? L2 ? L2 cache request misses
? L2 ? L2 data cache request misses
? IDR? ? decoded returns
? IDR? ? uOPs dispatched to a resource station



notes description
#1 This event can only be counted with CTR#0.
#2 This event can only be counted with CTR#1.
#3 This event is only defined for Pentium II or newer processors.
#4 This event is only defined for Pentium III processors.
#5 BR branches
CLK clocks
EBL external bus logic
FPU floating point unit
IDR instruction decoding and retirement
IFU instruction fetch unit
INT interrupts
L1d integrated L1 data cache
L2 integrated unified L2 cache
MO memory ordering
SRL segment register loads
ST stalls
MMX MMX unit
#6 MESI x?h = xxxxMESIb (bit 3..0 specify the MESI states)
CPU 00h=any, 20h=self (bit 5 specifies the event causing CPU for MP)
PORT x?h = xxxx3210b (bit 3..0 specify the ports #3..0)
OP 01h=packed multiply operations, 02h=packed shift operations, 04h=pack operations,
08h=unpack operations, 10h=packed logical operations, 20h=packed arithmetic operations
DIR 00h=direction MMX-to-FP, 01h=direction FP-to-MMX
SREG x?h = xxxxGFDEb (bit 3..0 specify GS, FS, DS, and ES)
SSE 0=packed and scalar, 1=scalar
SSE-MEM 0=PREFETCHNTA, 1=PREFETCHT1, 2=PREFETCHT2, 3=weakly ordered stores



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