IA-32 architecture
opcode encoding




short description
A direct address; no mod R/M byte; address of operand is encoded in instruction;
no base register, index register, or scaling factor can be applied
C reg field of mod R/M byte selects a control register
D reg field of mod R/M byte selects a debug register
E mod R/M byte follows opcode and specifies operand; operand is either a general register or a memory address;
if it is a memory address, the address is computed from a segment register and any of the following values:
a base register, an index register, a scaling factor, a displacement
F flags register
G reg field of mod R/M byte selects a general register
I immediate data; value of operand is encoded in subsequent bytes of instruction
J instruction contains a relative offset to be added to the instruction pointer register
M mod R/M byte may refer only to memory
O instruction has no mod R/M byte;
offset of operand is coded as a word or double word (depending on address size attribute) in instruction;
no base register, index register, or scaling factor can be applied; eg. MOV (A0..A3h)
P reg field of mod R/M byte selects a packed quadword MMX register
Q mod R/M byte follows opcode and specifies operand; operand is either an MMX register or a memory address;
if it is a memory address, the address is computed from a segment register and any of the following values:
a base register, an index register, a scaling factor, a displacement
R mod field of mod R/M byte may refer only to a general register
S reg field of mod R/M byte selects a segment register
T reg field of mod R/M byte selects a test register
V reg field of mod R/M byte selects a packed SIMD FP register
W mod R/M byte follows opcode and specifies operand; operand is either an SIMD FP register or a memory address;
if it is a memory address, the address is computed from a segment register and any of the following values:
a base register, an index register, a scaling factor, a displacement
X memory addressed by DS:SI register pair; eg. MOVS, CMPS, OUTS, LODS
Y memory addressed by ES:DI register pair; eg. MOVS, CMPS, INS, STOS, SCAS

short description
b byte (regardless of operand size attribute)
w word (regardless of operand size attribute)
d dword (regardless of operand size attribute)
q qword (regardless of operand size attribute)
o oword (regardless of operand size attribute)
c byte or word, depending on operand size attribute
v word or doubleword, depending on operand size attribute
a two word or two doubleword operands in memory, depending on operand size attribute (used only by BOUND)
p 32-bit or 48-bit pointer, depending on operand size attribute
s six-byte pseudo-descriptor

general instruction format (gray areas indicate optional parts) #1, #2
instruction prefix(es) opcode
byte(s)
mod
R/M
byte
16bit
32bit
SIB
byte
displacement immediate #4
P1 P2 P3 P4 O2 O1 D1 D2 D3 D4 I1 I2 I3 I4
SEG, REP, LOCK, 66h, 67h 0Fh xxh byte/word/dword byte/word/dword
notes description
#1 Note that the 15 byte instruction length limit (#GP exception) can only be exceeded by using non-redundant prefixes.
#2 Most 3DNow! instructions use a slighly modified format.
#3 Some SSE/SSE2 instructions use the immediate byte as a condition code.



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