IA-32 architecture
legacy stuff




 
legacy bus signals
 
name type description
A20M# input #1 level asynch #2 A20 mask #3, #4
FERR# output #5 level synch floating point error
IGNNE# input level asynch ignore numeric error
notes description
#1 Whether A20M# is honoured outside real mode, and/or inside SMM, is processor-specific.
#2 If A20M# is changed, and the effect is supposed to be immediate, then serialization must be enforced.
#3 If A20M# is asserted, A20 is masked, and odd megabytes map to the preceeding even megabytes.
#4 Exactly when A20 is masked is determined by whether eg. the caches are virtually or physically tagged.
The outcome, ie. the address driven on the processor's external bus, is independent though.
#5 The assertion of FERR# is independent of the state of CR0.NE and independent of the state of IGNNE#.
By default today's chipsets generate an IRQ13 in response to the assertion of FERR#.
Operating systems that want to use the #MF exception must either mask IRQ13, or disable its generation.
The former can be achieved by using the PIC mask registers; the latter is chipset-specific.
Last but not least, while STPCLK is asserted the Pending Break Event feature may use FERR# as an input.

 
KBC, PS/2, and A20M#
 

 
KBC
 
output port, pin 1
0 A20M# low asserted wrap memory
1 A20M# high deasserted flat memory

 
PS/2
 
system Port A, bit 1
0 KBC's A20M# depends depends
1 A20M# high deasserted flat memory


 
A20M#
 
KBC PS/2 A20M#
L 0 wrap L 0 (pass) L wrap
H 1 flat L 0 (pass) H flat #1
L 0 wrap H 1 flat H flat
H 1 flat H 1 flat H flat
note description
#1 This is the default state after RESET, which
gives (historical) precedence to the KBC.


 
FERR#, IGNNE#, IRQ13, and INTR
 
FERR#              
  #1 #5
 
IGNNE#  
  #4 #5
 
FP_IRQ  
  #2 #4
 
IRQ2  
  #2 #6
 
IRQ13  
  #2 #6
 
INTR  
  #3  
 
external logic for supporting FP exceptions
external logic for supporting FP exceptions
notes description
#1 If an unmasked FP exception is detected, then the processor asserts FERR#. Testing has shown that the FNCLEX, FNINIT, FNSAVE, and FNSTENV instructions pulse FERR# briefly, while all other FP and MMX instructions assert the signal (until #5).

In general there are two kinds of FERR# assertions: immediate and deferred. The former asserts the FERR# signal immediately, when the exception occurs, and then continues executing until the next FP instruction. By contrast, the latter defers the assertion of FERR# until the next FP instruction is executed.

Up to and including on the Intel P5-core processors, some FP instructions used immediate, others deferred reporting. Beginning with Intel's P6-core processors, all FP instructions use immediate reporting.

From an architectural standpoint always using deferred reporting is the cleaner solution, because it allows to predict where the corresponding INTR will occur.

Depending on the class of the "faulting" FP instruction, the state of IGNNE#, and the state of CR0.NE, the processor will respond as follows when it encounters the next FP instruction:

CR0.NE IGNNE# FP instruction response
0 deasserted wait freeze, then wait for an external interrupt
no-wait continue after sampling external interrupts
asserted either continue
1 ignored wait generate #MF exception
no-wait continue

#2 By default (ie. this is optional) the chipset generates an IRQ13 in response to the assertion of FERR#.
Depending on the actual implementation this may require some time, ie. cause a brief delay.
#3 The chipset asserts INTR, communicates vector PIC2_base+(13-8) to the processor (usually 75h), and then deasserts INTR. The processor enters the corresponding interrupt handler, specified by the IVT/IDT.
#4 The interrupt handler writes 00h to port F0h. In response the chipset asserts IGNNE#, allowing an interrupt handler to execute wait-class FP instructions. In addition the chipset clears the FP_IRQ input to PIC2. Both, IRQ13 and IRQ2 are however still latched in the PICs. They will be handled in step #6 (see below).
#5 The interrupt handler clears FSW.B/ES. This causes the deassertion of FERR#. In response the chipset deasserts IGNNE#. This will prevent any further unmasked FP exceptions from being ignored.
#6 The interrupt handler issues an EOI to both PICs, to get rid of the IRQ13 and the IRQ2, and then returns.



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