IA-32 architecture
table registers




 
GDTR, IDTR, LDTR, and TR
 
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0 internal descriptor cache
GDTR 32bit base res. 16bit limit access
rights
IDTR 32bit base res. 16bit limit access
rights
LDTR selector 32bit base 32bit limit access
rights
TR selector 32bit base 32bit limit access
rights



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