From Newsgroup: comp.sys.ibm.ps2.hardware

While meditating on the divine, I noticed an Oddity.

There are sixteen Arbitration level, 0 through F. You have four lines
for Arbitration level, ARB0-ARB3, available on the MC bus. That gives
you sixteen levels...

So, there are two system-only arbitration levels, -1 [NMI] and -2 [Refresh].

So... how does the system memory controller signal -2 to the CACP?
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