From Newsgroup: comp.arch

On Sun, 14 Jan 2024 14:30:51 -0500, EricP wrote:

Furthermore, the address and data registers and buses are 16 bits and
the high 16-bits are shared ...

No, in the 68000 family the A- and D- registers are 32 bits.

If you compare the earlier members with the 68020 and later, it becomes
clear that the architecture was designed as full 32-bit from the
beginning, and then implemented in a cut-down form for the initial 16-bit products. Going full 32-bit was just a matter of filling in the gaps.
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From Newsgroup: comp.arch

On 16/04/2024 02:35, Lawrence D'Oliveiro wrote:

On Sun, 14 Jan 2024 14:30:51 -0500, EricP wrote:

Furthermore, the address and data registers and buses are 16 bits and
the high 16-bits are shared ...

No, in the 68000 family the A- and D- registers are 32 bits.

If you compare the earlier members with the 68020 and later, it becomes
clear that the architecture was designed as full 32-bit from the
beginning, and then implemented in a cut-down form for the initial 16-bit products. Going full 32-bit was just a matter of filling in the gaps.

Yes, the 68000 was designed to have full support for 32-bit types and a
32-bit future, but (primarily for cost reasons) used a 16-bit ALU and
16-bit buses internally and externally. Some 68000 compilers had 16-bit
int, some had 32-bit int, and some let you choose either, since 16-bit
types could be significantly faster on the 68000 even though the general-purpose registers were 32-bit.


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From Newsgroup: comp.arch

David Brown wrote:

On 16/04/2024 02:35, Lawrence D'Oliveiro wrote:

On Sun, 14 Jan 2024 14:30:51 -0500, EricP wrote:

Furthermore, the address and data registers and buses are 16 bits and
the high 16-bits are shared ...

No, in the 68000 family the A- and D- registers are 32 bits.

If you compare the earlier members with the 68020 and later, it becomes
clear that the architecture was designed as full 32-bit from the
beginning, and then implemented in a cut-down form for the initial 16-bit
products. Going full 32-bit was just a matter of filling in the gaps.

Yes, the 68000 was designed to have full support for 32-bit types and a 32-bit future, but (primarily for cost reasons) used a 16-bit ALU and
16-bit buses internally and externally. Some 68000 compilers had 16-bit int, some had 32-bit int, and some let you choose either, since 16-bit
types could be significantly faster on the 68000 even though the general-purpose registers were 32-bit.

Yes, I was referring to its 16-bit internal bus structure.
This M68000 patent from 1978 shows it in Fig 2:

Patent US4296469 Execution unit for data processor using
segmented bus structure, 1978
https://patents.google.com/patent/US4296469A/en

Other M68000 patents (the last one US4514803 appears to be for
when it was reworked into the IBM XT/370 PC in 1983):

Patent US4307445 Microprogrammed control apparatus having
a two-level control store for data processor, 1978

Patent US4312034 ALU and Condition code control unit for
data processor, 1979

Patent US4325121 Two-level control store for microprogrammed
data processor, 1979

Patent US4514803 Methods for partitioning mainframe instruction sets, 1982

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From Newsgroup: comp.arch

EricP wrote:

Yes, I was referring to its 16-bit internal bus structure.
This M68000 patent from 1978 shows it in Fig 2:

Patent US4296469 Execution unit for data processor using
segmented bus structure, 1978
https://patents.google.com/patent/US4296469A/en

There are a number of interesting things about those segmented busses::
a) the busses were true-complement
b) the busses were precharged
c) the busses were coupled with 2 pass gates on either side of a
3 transistor sense amplifier
d) to copy data from one bus to the next buss one
1) opened up the pass gates on the active bus
2) fired the sense amplifier
3) opened up the pass gate to the next bus

So, in 7 transistors, one got::
a) bus to bus isolation
b) bus to bus data copy in either direction
c) and a bus flip-flop (fired sense amplifier)

This would take at least 30 transistors with todays technology
to do what they did in 7.
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