I'm studying datasheet of SST26VF080A. It's a SPI Quad Flash memory in standard 8 pin package.
I'm not sure I correctly understood the quad mode. It appears to me
two quad modes are supported: SPI Quad mode (IOC=1 in Configuration
Register) and SQI mode (after sending Enable Quad I/O command).
[...]
[...] I think the difference is only in the data transmitted by the
SPI master: opcode byte, address bytes and dummy bytes. In the first
case, they are transmitted serially on a single signal (SI/SIO0); in
SQI mode, they are transmitted serially on 4 signals (SIO[3-0]).
The behaviour on data transmitted by the serial Flash should be
exactly the same: they are transmitted on the 4 signals SIO[3-0].
Is my understanding correct?
I think the penalty of the first Quad mode respect the SQI mode is
very small.
I'm studying datasheet of SST26VF080A. It's a SPI Quad Flash memory in standard 8 pin package.
I'm not sure I correctly understood the quad mode. It appears to me two
quad modes are supported: SPI Quad mode (IOC=1 in Configuration
Register) and SQI mode (after sending Enable Quad I/O command).
For example, after setting IOC bit in Configuration Register I can use
SQOR command (SPI Quad Output Read) to output data from SIO[3:0] pins.
A similar behaviour can be obtained after enabling SQI mode (sending EQIO=Enable Quad I/O mode) and using High-Speed Read command (0x0B).
What is the difference? I think the difference is only in the data transmitted by the SPI master: opcode byte, address bytes and dummy
bytes. In the first case, they are transmitted serially on a single
signal (SI/SIO0); in SQI mode, they are transmitted serially on 4
signals (SIO[3-0]). The behaviour on data transmitted by the serial
Flash should be exactly the same: they are transmitted on the 4 signals SIO[3-0].
Is my understanding correct?
I think the penalty of the first Quad mode respect the SQI mode is very small.
On 04/04/2023 22:57, pozz wrote:
I'm studying datasheet of SST26VF080A. It's a SPI Quad Flash memory in
standard 8 pin package.
I'm not sure I correctly understood the quad mode. It appears to me
two quad modes are supported: SPI Quad mode (IOC=1 in Configuration
Register) and SQI mode (after sending Enable Quad I/O command).
For example, after setting IOC bit in Configuration Register I can use
SQOR command (SPI Quad Output Read) to output data from SIO[3:0] pins.
A similar behaviour can be obtained after enabling SQI mode (sending
EQIO=Enable Quad I/O mode) and using High-Speed Read command (0x0B).
What is the difference? I think the difference is only in the data
transmitted by the SPI master: opcode byte, address bytes and dummy
bytes. In the first case, they are transmitted serially on a single
signal (SI/SIO0); in SQI mode, they are transmitted serially on 4
signals (SIO[3-0]). The behaviour on data transmitted by the serial
Flash should be exactly the same: they are transmitted on the 4
signals SIO[3-0].
Is my understanding correct?
Yes.
In SPI Quad mode, /data/ is send 4 bits per clock (or twice that, for
double data rate pins). In SQI mode, /everything/ is sent 4 bits at a time.
I think the penalty of the first Quad mode respect the SQI mode is
very small.
It all depends on your clock speeds, your mix of reads and writes, your
wait states, the length of your transfers, etc. If you are doing big transfers then there will be little difference since most clocks are
data anyway. For lots of small transfers with few wait states, SQI will make a bigger difference.
(And if you are doing big data transfers, you might also want to enable double data rate on the pins, if your hardware supports it.)
Il 05/04/2023 17:52, David Brown ha scritto:
On 04/04/2023 22:57, pozz wrote:
I'm studying datasheet of SST26VF080A. It's a SPI Quad Flash memory
in standard 8 pin package.
I'm not sure I correctly understood the quad mode. It appears to me
two quad modes are supported: SPI Quad mode (IOC=1 in Configuration
Register) and SQI mode (after sending Enable Quad I/O command).
For example, after setting IOC bit in Configuration Register I can
use SQOR command (SPI Quad Output Read) to output data from SIO[3:0]
pins.
A similar behaviour can be obtained after enabling SQI mode (sending
EQIO=Enable Quad I/O mode) and using High-Speed Read command (0x0B).
What is the difference? I think the difference is only in the data
transmitted by the SPI master: opcode byte, address bytes and dummy
bytes. In the first case, they are transmitted serially on a single
signal (SI/SIO0); in SQI mode, they are transmitted serially on 4
signals (SIO[3-0]). The behaviour on data transmitted by the serial
Flash should be exactly the same: they are transmitted on the 4
signals SIO[3-0].
Is my understanding correct?
Yes.
In SPI Quad mode, /data/ is send 4 bits per clock (or twice that, for
double data rate pins). In SQI mode, /everything/ is sent 4 bits at a
time.
Ok, now suppose you would like to work in SQI mode. During startup you
send the Enable SQI command over a single data line (MOSI). From now on,
you can send SQI commands using 4 data lines even for command code byte
(two clocks).
However you can't be sure at startup the Flash is in normal SPI mode.
This happens when you power up the board, but it's not true when the MCU resets itself (for example, for watchdog).
What could be the initialization process to bring the SPI Flash in SQI
mode at startup, without knowing if it is already in SQI mode or not?
I think the penalty of the first Quad mode respect the SQI mode is
very small.
It all depends on your clock speeds, your mix of reads and writes,
your wait states, the length of your transfers, etc. If you are doing
big transfers then there will be little difference since most clocks
are data anyway. For lots of small transfers with few wait states,
SQI will make a bigger difference.
(And if you are doing big data transfers, you might also want to
enable double data rate on the pins, if your hardware supports it.)
What do you mean with DDR here?
Ok, now suppose you would like to work in SQI mode. During startup you send the
Enable SQI command over a single data line (MOSI). From now on, you can send SQI commands using 4 data lines even for command code byte (two clocks).
However you can't be sure at startup the Flash is in normal SPI mode. This happens when you power up the board, but it's not true when the MCU resets itself (for example, for watchdog).
What could be the initialization process to bring the SPI Flash in SQI mode at
startup, without knowing if it is already in SQI mode or not?
I think the penalty of the first Quad mode respect the SQI mode is very small.
It all depends on your clock speeds, your mix of reads and writes, your wait
states, the length of your transfers, etc. If you are doing big transfers >> then there will be little difference since most clocks are data anyway. For
lots of small transfers with few wait states, SQI will make a bigger difference.
(And if you are doing big data transfers, you might also want to enable
double data rate on the pins, if your hardware supports it.)
What do you mean with DDR here?
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